`timescale 1ns / 1ps
//****************************************VSCODE PLUG-IN**********************************//
//----------------------------------------------------------------------------------------
// IDE :                   VSCODE     
// VSCODE plug-in version: Verilog-Hdl-Format-2.5.20240605
// VSCODE plug-in author : Jiang Percy
//----------------------------------------------------------------------------------------
//****************************************Copyright (c)***********************************//
// Copyright(C)            Please Write Company name
// All rights reserved     
// File name:              
// Last modified Date:     2024/06/10 14:48:02
// Last Version:           V1.0
// Descriptions:           
//----------------------------------------------------------------------------------------
// Created by:             Please Write You Name 
// Created date:           2024/06/10 14:48:02
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// Version:                V1.0
// TEXT NAME:              rst_ctrl.v
// PATH:                   D:\FPGA\ov5640_series\ov5640_cfg\rtl\my_rtl\top\rst_ctrl.v
// Descriptions:           
//                         
//----------------------------------------------------------------------------------------
//****************************************************************************************//

module rst_ctrl(
    input     clk            ,
    input     ddr_ui_clk     ,
    input     sys_rst_n      ,
    output    ddr_rst_n      ,
    output    cam_rst_n  ,
    output    fifo_rst_n     
);
reg [7:0] cnt;
reg [7:0] ddr_cnt;

assign ddr_rst_n = sys_rst_n;
assign cam_rst_n = fifo_rst_n;
assign fifo_rst_n = (cnt < 8'd2) ? 1'd0 : 1'd1;                                                      
always @(posedge clk or negedge sys_rst_n)begin                                        
    if(~sys_rst_n)  
        cnt <= 8'd0;                        
    else if(cnt == 8'd2)
        cnt <= cnt; 
    else if(ddr_cnt == 8'd100)
        cnt <= cnt + 8'd1;
    else
        cnt <= cnt;                          
end    

always @(posedge ddr_ui_clk or negedge sys_rst_n)begin                                        
    if(~sys_rst_n)  
        ddr_cnt <= 8'd0;                        
    else if(ddr_cnt == 8'd100)
        ddr_cnt <= ddr_cnt; 
    else
        ddr_cnt <= ddr_cnt + 8'd1;                     
end
endmodule